Tegra132: set TZDRAM_BASE to 0xF5C00000

The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.

Signed-off-by: Varun Wadekar <[email protected]>

diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md
index 6c76dd109eeadf6f0e8f472552cea13028f8e2e0..d8e8ec63e8dd6afbe39ff71490ca49c5424bf530 100644 (file)
--- a/docs/plat/nvidia-tegra.md
+++ b/docs/plat/nvidia-tegra.md
@@ -59,6 +59,9 @@ Preparing the BL31 image to run on Tegra SoCs
 'CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
 TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> all'
 
+Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>'
+to the build command line.
+
 Power Management
 ================
 The PSCI implementation expects each platform to expose the 'power state'

diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 1be13e919a2571d5a62d1923581cc6d3019390ee..69d62964fe9b08482b9085ece50fbee8ff2a23b0 100644 (file)
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -31,7 +31,7 @@
 TEGRA_BOOT_UART_BASE           := 0x70006300
 $(eval $(call add_define,TEGRA_BOOT_UART_BASE))
 
-TZDRAM_BASE                    := 0xF1C00000
+TZDRAM_BASE                    := 0xF5C00000
 $(eval $(call add_define,TZDRAM_BASE))
 
 PLATFORM_CLUSTER_COUNT         := 1